library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mul4 is
    Port ( datain : in  STD_LOGIC_VECTOR (7 downto 0);
           multiplier : in  STD_LOGIC_VECTOR (3 downto 0);
           dataout : out  STD_LOGIC_VECTOR (7 downto 0));
end mul4;

architecture Behavioral of mul4 is
	signal datain_x2, datain_x4, dataout_msb, dataout_lsb : std_logic_vector(7 downto 0);
begin
	mul_x2: entity work.mul(Behavioral)
		port map (datain => datain, multiplier => "10", dataout => datain_x2);
	mul_x4: entity work.mul(Behavioral)
		port map (datain => datain_x2, multiplier => "10", dataout => datain_x4);
	mul_msb: entity work.mul(Behavioral)
		port map (datain => datain_x4, multiplier => multiplier(3 downto 2), dataout => dataout_msb);
	mul_lsb: entity work.mul(Behavioral)
		port map (datain => datain, multiplier => multiplier(1 downto 0), dataout => dataout_lsb);

	dataout <= dataout_msb xor dataout_lsb;	-- dodanie wynikow z dwoch mnozarek
end Behavioral;

